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Showing 2 open source projects for "without code"
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Project Planning and Management Software | PlanviewPlanview® ProjectAdvantage (formerly Sciforma) is an enterprise-centric project and portfolio management (PPM) software designed to enable change, drive innovation, and lead in a company's digital transformation. With ProjectAdvantage, teams can strategically track and monitor project data in order to make relevant decisions. It offers multiple features focused on strategic management, functional management, and execution management. A highly scalable and cost-effective solution, ProjectAdvantage is available in various deployment models.
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The Most Awarded Employee Time Clock SoftwareCloud based time clock solution that pre-populates reports for payroll. Employees can punch in on their desktop or mobile devices. Punching in & out is intuitive for your employees & easy for you to view & export time. Employees can clock in using a browser or our Google, iOS, & Android apps. You can view who's working, their GPS position or even limit where they can punch. We integrate with QuickBooks, ADP, Paychex, & SurePayroll while also offering Excel exports. Advanced features such as PTO Accrual Tracking, Punch Rounding, Job Codes, QR Codes, Automatic Breaks, & SSO are all included in our cloud based time clock.
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UniSIMD-assembler
SIMD macro assembler unified for ARM, MIPS, PPC and x86
...It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ... -
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Code Red Sim
A low-power ISA design and simulator for a 2010 IEEE competition
This is a student project designed to compete in the 2010 IEEE Computer Society Student Competition: http://www.computer.org/portal/web/competition/2010competition The Code Red architecture is designed for extremely lower power environments, like distributed sensor networks. Included is a design of that architecture, a Java-based simulator, an implementation (without vector instructions) designed as a Logisim circuit (http://ozark.hendrix.edu/~burch/logisim/), and more. The name "Code Red" comes from our team name, the Red Team. ...
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