Search Results for "javaee code generator"
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Showing 9 open source projects for "javaee code generator"
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Dynamic Work and Complex Project Management Platform | QuickbaseOur no-code platform lets you easily create, connect, and customize enterprise applications that fix visibility and workflow gaps without replacing a single system.
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The top-rated AI recruiting platform for faster, smarter hiring.Humanly is an AI-first recruiting platform that helps talent teams hire in days, not months—without adding headcount. Our intuitive CRM pairs with powerful agentic AI to engage and screen every candidate instantly, surfacing top talent fast. Built on insights from over 4 million candidate interactions, Humanly delivers speed, structure, and consistency at scale—engaging 100% of interested candidates and driving pipeline growth through targeted outreach and smart re-engagement. We integrate seamlessly with all major ATSs to reduce manual work, improve data flow, and enhance recruiter efficiency and candidate experience. Independent audits ensure our AI remains fair and bias-free, so you can hire confidently.
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CircuiTikZ Generator
This software is a tool for designing electronic circuits using LaTeX.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library. -
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AUDio MEasurement System
PC based Oscilloscope and Spectrum analyzer using sound card
AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md -
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at... -
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QTronics ToolSet
Includes tools for performing electronic calculations.
...Ohms, Kirchhoff, Parralel Res., Voltage Divider, Wheatstone, Reistor Color, Zener diode, LED resistor, capacitor, inductor, transformer, capacitive reactance, Transformerless adaptor, R-C Time calculator, Flip-Flop, NE555 calculator, TL431 calculator, 78XX, LM317, Current Limiter, Transistor Regulator, Current Mirror, Battery charge calculations, transistor calculator, mosfet, pass filters, opamp, schmitt-trigger, signal generator, darlington-sziklai, ladder DAC, Long Tailed Pair, Buck-Boost, Logic Gates, Antenna Length, Trace Size, Decibell, Unit Converter, Cable Dia, Electronic Filters, 7 Segment digital, toroid core, smd code, resistor standard finder, heatsink calculator. My Github: https://github.com/shampuan/QTronics-Toolset -
Polygon Software | Apparel Software | PLM and ERP SolutionsPolyPM is an integrated enterprise resource planning (ERP) and product lifecycle management (PLM) solution developed by Polygon Software. Built for small to medium-sized apparel manufacturers, PolyPM enables businesses to integrate all aspects of the product development, supply chain and production processes, as well as instantly access all their style and manufacturing information anywhere in the world. This allows businesses to shorten time-to-market, incur lower development costs, and improve customer service and worker productivity.
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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PikLoops is a simple KDE program used to generate assembly time delays for Microchip microcontrolers using Microchip instructions.
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UVE
Unified Verification Environment
...UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. ... -
MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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