Open Source Java Electronic Design Automation (EDA) Software - Page 3

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

A Java based Backus-Naur test API

This project has been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home It includes two libraries for working with decision diagrams: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD

A tool to read and browse records from a GDSII stream file.

A GDSII database parser and stream integrity verifier

Jove - The Open Verification Environment for the Java (TM) Platform

This is a very powerful Schematic and PCB layout tool for electronic Engineer. It is very easy to use. Coming version will add the SPICE features as well as the 3D model. This tool is target for single user, so all the things such as Schematic, PCB layout, SPICE model, 3D models are all combined into a single project file "*.prj" in ZIP file format. Anyone should able to explore and see the structure of files using any zip tool.

Juno - OpenVera (TM) to Jove Translator

The aim of this project is to implement a channel router using the left-edge algorithm.

LogicS is an EDA (Electronic Design Automation) desktop program, targeting digital circuits: designing, edtiting & simulating them. The user will be provided with a user-friendly environment for doing this (adding logic gates, creating links, simulating)

Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.

The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.

NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.

Nocmaker is a tool for the design space exploration tool to help in the design of Network on chips. Noc Maker is based on JHDL.

ODog

This JAVA library give the possibility to have a CANVAS object in JAVA SWING graphical applications, including CANVAS tools such as hand-tool, linker-tool, group-tool like VISIO(TM) application. The library take advantage of Java2D packages to reach a

This project is aimed to build an Open Source Manufacturing Execution System based on J2EE, JBoss technology. Intesity based optimization

This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).

PCB-Tools is a system independent, a Java programmed Eclipse-RCP application for developing circuit diagrams and printed circuit boards. It uses Eclipse Graphical Editor Framework (GEF) to draw diagrams and layouts.

A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.

PIC Development Studio is a simulator for the PIC16F84 microcontroller. It also provides a plugin framework making it possible to develop custom components. A library of ready-made components is included.

This project provides a 'brute-force' search for optimum assembler fragments for Microchip Technology Inc's mid-range PIC processor range.

Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.