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Showing 16 open source projects for "opensource java code"
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Network Performance Monitoring | StatseekerUsing just a single server or virtual machine, Statseeker can be up and running within minutes, and discovering your entire network in less than an hour, without any significant effect on your bandwidth availability.
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Runn is a modern resource and capacity planning platform that gets remote teams on the same page.Runn has a modern and easy-to-use interface that provides your team with a shared view of all the people and projects in your organization. Plan new work alongside existing projects and instantly see how changes to your plans and resourcing affect your company’s bottom line. Runn is intuitive to use and lets you quickly schedule work using simple drag and drop functionality. Runn also allows you to collaborate with your co-workers in real-time, seeing updates live without having to refresh your browser. Runn combines resource and capacity planning with integrated actual tracking and powerful forecasting to deliver meaningful insights and a full picture of your organization.
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
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myNetPCB
Community driven PCB Layout and Schematic capture software
PCB Layout and Schematic capture tool for Win/Linux/Mac. Source code at https://github.com/sergei-iliev/myNetPCB -
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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Safety Compliance Made EasyIdeally designed for business that deals with Construction, Oil & Gas, Mining, Manufacturing, Mechanical, Electrical, Plumbing, Heating, and Excavating, SiteDocs is a perfect solution for any size business looking to modernize the way Safety Compliance is organized.
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JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
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dvkit
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code -
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
...AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
The most trusted software in constructionHCSS provides easy-to-use software built for construction companies that want to win more work, work smarter, and boost profits. For nearly 40 years, we've helped heavy civil contractors, infrastructure builders, and utility companies improve operations, from estimating and project management to field tracking, equipment maintenance, and safety. Tools like HeavyBid, HeavyJob, and HCSS Safety are built for the field and designed to work together, giving your team real-time visibility, tighter cost control, and better job outcomes. With 45+ accounting integrations and customizable APIs, HCSS fits seamlessly into your tech stack. We regularly update our software based on feedback from real crews, ensuring it fits the way your team works. Backed by award-winning 24/7/365 support and a proven implementation process, HCSS helps reduce risk, cut inefficiencies, and deliver fast ROI. If you're ready to grow your business and gain a competitive edge, HCSS is the partner that gets you there.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.
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