Search Results for "python code generator"
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Showing 17 open source projects for "python code generator"
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CircuiTikZ Generator
This software is a tool for designing electronic circuits using LaTeX.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library. -
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AUDio MEasurement System
PC based Oscilloscope and Spectrum analyzer using sound card
AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md -
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at... -
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QTronics ToolSet
Includes tools for performing electronic calculations.
...Ohms, Kirchhoff, Parralel Res., Voltage Divider, Wheatstone, Reistor Color, Zener diode, LED resistor, capacitor, inductor, transformer, capacitive reactance, Transformerless adaptor, R-C Time calculator, Flip-Flop, NE555 calculator, TL431 calculator, 78XX, LM317, Current Limiter, Transistor Regulator, Current Mirror, Battery charge calculations, transistor calculator, mosfet, pass filters, opamp, schmitt-trigger, signal generator, darlington-sziklai, ladder DAC, Long Tailed Pair, Buck-Boost, Logic Gates, Antenna Length, Trace Size, Decibell, Unit Converter, Cable Dia, Electronic Filters, 7 Segment digital, toroid core, smd code, resistor standard finder, heatsink calculator. My Github: https://github.com/shampuan/QTronics-Toolset -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the... -
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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dvkit
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code -
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pyGerber2Gcode
Python Gerber to G-code converter
pyGerber2Gcode is a Pyhon based simple Gerber to G-code converter. -
B2i offers full-service IR websites, widgets and pluginsB2i Technologies provides the most robust and versatile tools to manage your Corporate website, Investor Relations website and email communications. Our Investor Relations Software solutions work through automation and implements into existing systems with ease in only a few steps. Our solutions not only help you stay compliant but save valuable time while reporting and delivering critical financial data and press release activities to investors. B2i's Investor Relations Solution provides highly reliable and customizable data for corporate websites including press releases, stock data, charting, and SEC filings within SOX compliance standards. Our investor relations software displays real-time data on your website without requiring additional work on your behalf. Once you have completed your filings and press releases they are automatically loaded onto your website and formatted for easy access.
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
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PikLoops is a simple KDE program used to generate assembly time delays for Microchip microcontrolers using Microchip instructions.
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Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Please post any support requests or bug reports to the tracking system.
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UVE
Unified Verification Environment
...UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. ...
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