Search Results for "sourceforge.net/projects/winpython/files/winpython_3.8/3.8.10.0/winpython64-3.8.10.0.7z"

x
Sort By:

Showing 8 open source projects for "sourceforge.net/projects/winpython/files/winpython_3.8/3.8.10.0/winpython64-3.8.10.0.7z"

View related business solutions
Electronic Design Automation (EDA) VHDL/Verilog Clear Filters & Widen Search
  • Jscrambler: Pioneering Client-Side Protection Platform Icon
    Jscrambler: Pioneering Client-Side Protection Platform

    Jscrambler offers an exclusive blend of cutting-edge first-party JavaScript obfuscation and state-of-the-art third-party tag protection.

    Jscrambler is the leader in Client-Side Protection and Compliance. We were the first to merge advanced polymorphic JavaScript obfuscation with fine-grained third-party tag protection in a unified Client-Side Protection and Compliance Platform. Our integrated solution ensures a robust defense against current and emerging client-side cyber threats, data leaks, and IP theft, empowering software development and digital teams to innovate securely. With Jscrambler, businesses adopt a unified, future-proof client-side security policy all while achieving compliance with emerging security standards including PCI DSS v4.0. Trusted by digital leaders worldwide, Jscrambler gives businesses the freedom to innovate securely.
    Learn More
  • Diagnose and Resolve IT Issues in Real Time Icon
    Diagnose and Resolve IT Issues in Real Time

    Engage your employees and agents more efficiently with ScreenMeet as a seamless extension of your existing IT Service Delivery Platform.

    ScreenMeet’s unique combination of video calling, screen share, and remote desktop functionality lets you quickly diagnose hardware and software issues with no frustration.
    Learn More
  • 1

    VlibTools

    Tools and libraries for use with systemc and verilog

    Tool suite and libraries for developing system-c models. Tools for managing RTL projects.
    Downloads: 0 This Week
    Last Update:
    See Project
  • 2
    bel_fft

    bel_fft

    FFT co-processor in Verilog based on the KISS FFT

    ...However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.
    2 Reviews
    Downloads: 2 This Week
    Last Update:
    See Project
  • 3
    CoreTML framework
    CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
    Downloads: 0 This Week
    Last Update:
    See Project
  • 4
    FSMDesigner
    FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
    Downloads: 7 This Week
    Last Update:
    See Project
  • Secure User Management, Made Simple | Frontegg Icon
    Secure User Management, Made Simple | Frontegg

    Get 7,500 MAUs, 50 tenants, and 5 SSOs free – integrated into your app with just a few lines of code.

    Frontegg powers modern businesses with a user management platform that’s fast to deploy and built to scale. Embed SSO, multi-tenancy, and a customer-facing admin portal using robust SDKs and APIs – no complex setup required. Designed for the Product-Led Growth era, it simplifies setup, secures your users, and frees your team to innovate. From startups to enterprises, Frontegg delivers enterprise-grade tools at zero cost to start. Kick off today.
    Start for Free
  • 5

    ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. ...
    Downloads: 4 This Week
    Last Update:
    See Project
  • 6
    vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
    Downloads: 0 This Week
    Last Update:
    See Project
  • 7
    Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.
    Downloads: 0 This Week
    Last Update:
    See Project
  • 8

    Labcoat: Cleanroom Apps for SuperWikia

    Labcoat; the VHDL graphic emulator.

    ...Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.
    Downloads: 0 This Week
    Last Update:
    See Project
  • Previous
  • You're on page 1
  • Next

Related Searches

Related Categories

MongoDB Logo MongoDB