Search Results for "https"

...Executables can be downloaded for Windows, Mac, Linux, and Android; source code is also available. An active community maintains and extends the system. Website: https://maxima.sourceforge.io Additional add-on packages for Maxima can be found at: https://github.com/maxima-project-on-github/maxima-packages

AudeLA is a TCL extension aimed at providing amateur astronomers with image processing, telescope controling, ccd camera driving, and various astronomical algorithms. Web site : https://sourceforge.net/p/audela/wiki/fr_accueil Web site : https://sourceforge.net/p/audela/wiki/en_welcome

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API...

1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity...

...Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed. Can be found also on github: https://github.com/StefanSchippers/xschem

...SpecTcl has been developed under NSF grant PHY-9528844 and DOE grant DE-SC0000661 Note that as of July 2023, all future development and release packages will be occur at https://github.com/FRIBDAQ/SpecTcl

The NSCL Data Acquisition system is a general purpose nuclear physics data acquisition system in use at several university labs and, of course, the National Superconducting Cyclotron Laboratory at Michigan State University. The development of the NSCLDAQ is currently funded by DOE grant DE-SC0000661 Note that as of July, 2023 all development and release packages will be hosted at https://github.com/FRIBDAQ/NSCLDAQ

Tcl/Tk support for the EPICS control system along with EPICS aware megawidgets. Note that as of September 27, 2023, development and new releases of this project will occur on github. See: https://github.com/FRIBDAQ/EpicsTcl

Please note that OWFS source code, and all Issue/Tickets/merge requests have now been moved to https://github.com/owfs/owfs/. Developer mailing lists will still be kept at Sourceforge. ---- OWFS -- 1-Wire file system. Use the Dallas 1-Wire and iButton chips with standard filesystem commands. Create temperature loggers. Monitor everything. OWHTTPD -- same system, only used as a light weight web server. OWFS is also ported to embedded routers, Mac OSX and Windows.

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered

HQP was migrated to git. See https://github.com/omuses/hqp