Open Source VHDL/Verilog Software - Page 3

This project follows The Elements of Computing fundamentals book, except all the hardware is written in Verilog . This is currently a hobby project, eventually I plan on implementing this onto a FPGA and tinkering with it some more.

Controlix is a virtual-circuit based operating system written in RTL.

CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).

We are currently working with professors Bruce Land and Paul Kintner to develop a hardware mobile GPS receiver on an FPGA, capable of receiving L1 civilian GPS signals in real time.

Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application

This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture.

A collection of useful software packages to perform engineering tasks, especially electrical engineering and chip design. All packages come as shrink-wrapped installers for Apple's Mac OS X.

This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.

The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital electronics. Neutron detection is also foreseen via the collaboration with the NEUTROMANIA group. FAZIA is designed to operate at stable and radioactive beams facilities like LNL-Legnaro, LNS-Catania in Italy, GANIL-SPIRAL and SPIRAL2 in France, GSI-FAIR in Germany in the horizon 2010-2015. The availability of the european radioactive beam facility EURISOL expected in the period 2015-2020 will also be a major opportunity for the FAZIA community.

Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.

The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard.

The aim of this project is to develop a Graphic Processing Unit core targeting FPGA implementation.

Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor

FPGAmer is a framework to develop embedded games. Our development platform is the Xilinx University Program Virtex-II-Pro but not limited to that. FPGAmer includes custom hardware components plus a custom software framework and some sample games.

A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.

Student Project

An open-hardware and -firmware project that implements a USB-input fully-digital class-D audio amplifier. All processing is done on FPGA, including the USB-physical, USB-SIE, HID interface, clock-recovery, bus voltage regulation, noise-shaping and PWM output. A Microchip PIC based remote control is also included. The remote maps to the media buttons of the USB HID interface. The volume control, next track, previous track, stop and play/pause functions are supported.

the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol

The purpose of this simple DIY project is to build an electronic circuit that received the GPS time signal, convert it to the radio-controlled clock format, and transmit that signal to the clock. Once built, there is no need for setup and maintenance, all you need is put this unit close to the window to receive GPS signal, and it will transmit the time signal to your radio-controlled clock.

This project aims at creating an open-source SoC that will support the Google TV platform.

GalaxyIP (Galaxy Intellectual Property Cores) is a project devoted to accommodate a set of IP-Cores for embedded SoC development, based on the processor code named Voyager (StarTrek and the space probes).

Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.

Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.

Gwyscope is a low cost, open hardware, Digital Signal Processor (DSP) suitable for Scanning Probe Microscopy measurements, focusing on demonstrating the concept of adaptive scanning, general XYZ data acquisition and statistical data processing on the controller level. More details can be found in: M. Valtr et al., Scanning Probe Microscopy controller with advanced sampling support, HardwareX, Volume 15, e00451 https://www.hardware-x.com/article/S2468-0672(23)00058-5/fulltext It is based on a low cost FPGA board Red Pitaya and additional high bit depth AD and DA converters. When put together with the AFM scanning hardware (sensor, scanner and their amplifiers) and user interface software it can serve as a standalone SPM system. Otherwise, it can serve as a sub-module for a custom built SPM system, e.g. providing the feedback loop mechanism only. Finally, it can be used as a board for developing advanced sampling techniques, which was the primary goal.

The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.