Search Results for "compiler python linux"
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Showing 17 open source projects for "compiler python linux"
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SOCRadar Extended Threat Intelligence PlatformSOCRadar Extended Threat Intelligence, a natively single platform from its inception that proactively identifies and analyzes cyber threats with contextual and actionable intelligence.
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CloudZero: The Cloud Cost Optimization PlatformCloudZero is the leader in proactive cloud cost efficiency. We enable engineers to build cost-efficient software without slowing down innovation. CloudZero's next-generation cloud cost optimization platform automates the collection, allocation, and analysis of cloud costs to uncover savings opportunities and improve unit economics. We are the only platform that enables companies to understand 100% of their operational cloud spend and take an engineering-led approach to optimizing that spend. CloudZero is used by industry leaders worldwide, such as Coinbase, Klaviyo, Miro, Nubank, and Rapid7.
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GHDL
VHDL 2008/93/87 simulator
...By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine. -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
AWS EC2 FPGA Development Kit is a set of development and runtime tools to develop, simulate, debug, compile and run hardware-accelerated applications on Amazon EC2 F1 instances. It is distributed between this GitHub repository and FPGA Developer AMI - Centos/AL2 provided by AWS with no cost of development tools. After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable... -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
Intelligent testing agents | Checksum.aiCoding agents write the code. Checksum runs it—continuously testing against real APIs, real data, real edge cases—before it ever reaches production.
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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COFILOS
A Development Framework for Coldfire
Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO... -
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A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
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BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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Stigg | SaaS Monetization and Entitlements APIA monetization platform is a standalone middleware that sits between your application and your business applications, as part of the modern enterprise billing stack. Stigg unifies all the APIs and abstractions billing and platform engineers had to build and maintain in-house otherwise. Acting as your centralized source of truth, with a highly scalable and flexible entitlements management, rolling out any pricing and packaging change is now a self-service, risk-free, exercise.
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation *... -
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A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction.
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Labcoat: Cleanroom Apps for SuperWikia
Labcoat; the VHDL graphic emulator.
Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.
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