Showing 27 open source projects for "linux command"

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  • 1
    Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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    Downloads: 668 This Week
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  • 2
    A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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  • 3
    Controlix

    Controlix

    An operating system written in RTL

    Controlix is a virtual-circuit based operating system written in RTL.
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  • 4

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
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  • 5
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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  • 6
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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    Downloads: 11 This Week
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  • 7

    ghdl-updates

    GHDL - a VHDL simulator

    GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.
    Downloads: 17 This Week
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  • 8

    PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
    Downloads: 2 This Week
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  • 9

    COFILOS

    A Development Framework for Coldfire

    Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO...
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  • 10
    CoreTML framework
    CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
    Downloads: 0 This Week
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  • 11

    ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as...
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  • 12
    Pulse Programmer
    A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
    Downloads: 2 This Week
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  • 13

    Partially Reconfigurable Hardware

    Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs

    This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating...
    Downloads: 0 This Week
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  • 14

    smPla

    SystemVerilog module to substitute Verilog PLA system tasks.

    SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane.
    Downloads: 0 This Week
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  • 15
    xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
    Downloads: 0 This Week
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  • 16
    VSYML is an automated symbolic simulator for VHDL designs.
    Downloads: 0 This Week
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  • 17
    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
    Downloads: 0 This Week
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  • 18
    The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
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  • 19
    A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform
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  • 20
    BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.
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    Downloads: 3 This Week
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  • 21
    Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications.
    Downloads: 0 This Week
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  • 22
    This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
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  • 23
    Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.
    Downloads: 0 This Week
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  • 24
    System on Chip design generator.
    Downloads: 0 This Week
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  • 25
    Tool-independent Makefile generator for VHDL models.
    Downloads: 0 This Week
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