Recent changes to bugs

Compilation error with JK flipflop module

Siva Chandra — Thu, 01 Mar 2007 06:45:33 -0000

There has been a slip-up in the constructor of the JK flipflop module. The function onStateChange needs a parameter. Currently, the function is called in the constructor without a parameter. It has to be changed to

onStateChange(4)

since 4 is the reset port Id.

This will be corrected in the next release numbered 0.0.53.

Problem with FrequencyDivider Class

Siva Chandra — Sat, 17 Feb 2007 10:32:28 -0000

The FrequencyDivider class is dividing the input frequency by twice the factor asked for. This bug will be fixed with the 0.0.52 release.

Problem with using multiple/different assignment delays

Siva Chandra — Tue, 19 Dec 2006 04:56:07 -0000

There is an issue due to which using multiple/different assignment delays for a single line will cause unknown/unexpected behavior. Kindly refrain from using multiple/different assignment delays for a any single line. Use only one unique assignment delay for a given bus line.

The cause of this bug has been discovered. A release numbered 0.0.49.1 will be made in a few days to fix it. I remind again, until the bug-fix release is made, kindly use use only one unique assignment delay for a given bus line.

Problem with VCD file if only one variable is being dumped

Siva Chandra — Mon, 04 Dec 2006 04:35:43 -0000

If a user requests dumping of only one variable into a VCD file for a simulation, then that request is not being entertained. A VCD file is being created, but it does not contain temporal information. Hence, this file fails to get displayed with GTKWave.

0.0.3: Problems with mixing delay and non-delay elements

Siva Chandra — Tue, 24 Oct 2006 04:55:31 -0000

Mixing circuit elements having delay with circuit
elements having no delay is making the circuit
sensitive to the order in which the circuit elements
are declared in the program. However, this problem will
not arise if all the circuit elements in the system
have a non-zero delay.

This is due to the improper way of implementing
parallelly running circuit elements using a sequential
simulation system. This can be rectified by
incorporating a defualt hidden delay mechanism for all
the circuit elements. This delay is called hidden as it
is hidden from the user. The user will not feel this delay.

Bus locking after bus concatenation

Siva Chandra — Mon, 09 Oct 2006 11:47:44 -0000

Consider the following code:

Bus<1> a, b, c;
Bus<3> d = a*b*c;

If we lock the bus d by a call d.lock(), the busses a,
b and c dont get locked.