Search Results for "gem5 cache memory simulator"

The gem5-STNoC model available here (https://sourceforge.net/projects/gem5-stnoc) in alpha version is adapted from the gem5 Garnet Fixed Pipeline as a cycle-approximate NoC model based on STMicroelectronics STNoC backbone specifications. It supports several mechanisms implemented at the STNoC Network Interface, such as NoC Firewall and preliminary Memory Interleaving. The model is freeware covered by standard gem5 license. Development has been partly supported by EU-ICT projects DREAMS and TRESCCA.

Project implementing simulator of virtual CPU with additional tools. Application written in C# 4, .Net Framework 4.0 , Visual Studio 2010 Features: - IDE- like environment with MDI interface - Customizable (plug- ins) architecture: instruction sets, directives, registers, additional MDI windows - Own assembler using Intel syntax producing binary programs - Simulation of i386- like CPU operating on multi- level cache and RAM - Simulation of debugger and memory view - Features of simple OS: scheduling, multi- tasking by context switching, memory management Currently available version considered "initial". ...

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

JPACS, Java Processor and Cache Simulator, was developed to give a simple and clear tool to simulate a processor with a complete associative memory cache at ISA level, using direct memory access or using a program written in assembly.