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Showing 17 open source projects for "testbench"
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Attack Surface Management | Criminal IP ASMCriminal IP’s Attack Surface Management (ASM) is a threat-intelligence–driven platform that continuously discovers, inventories, and monitors every internet-connected asset associated with an organization, including shadow and forgotten resources, so teams see their true external footprint from an attacker’s perspective. The solution combines automated asset discovery with OSINT techniques, AI enrichment and advanced threat intelligence to surface exposed hosts, domains, cloud services, IoT endpoints and other Internet-facing vectors, capture evidence (screenshots and metadata), and correlate findings to known exploitability and attacker tradecraft. ASM prioritizes exposures by business context and risk, highlights vulnerable components and misconfigurations, and provides real-time alerts and dashboards to speed investigation and remediation.
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Powerful Website Security | Continuous Web Threat PlatformReflectiz is a comprehensive web exposure management platform that helps organizations proactively identify, monitor, and mitigate security, privacy, and compliance risks across their online environments. Designed to address the growing complexity of modern websites, Reflectiz provides full visibility and control over first, third, and even fourth-party components, such as scripts, trackers, and open-source libraries that often evade traditional security tools.
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Laravel Testbench Component
Laravel Testing Helper for Packages Development
Testbench Component is the de-facto package that has been designed to help you write tests for your Laravel package. -
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...This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)
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VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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SVUnit
Systemverilog Unit Test Framework
SVUnit is a unit test framework for developers writing code in systemverilog. Verify systemverilog modules, classes and interfaces in isolation with SVUnit to eliminate bugs before they infest your design! -
The Receptionist for iPad | the Original Visitor Management SystemThe Receptionist for iPad is visitor management software that allows users to calm the chaos of the front office. Our digital check-in solution is customizable to your needs; from your company branding, to configurable buttons and drag-and-drop-design badge printing. Effectively manage and track everyone who comes to your workspace and store the information securely in the cloud: no more paper visitor log!
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AS2CBench
Accelerated S2CBench benchmarks
Accelerated version of the Synthesizable SystemC benchmark suite (S2CBench), mapped onto Terasic's DE1-SoC FPGA board. Testbench runs on the ARM Cortex-A processor DUT is mapped onto the programmable logic. -
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cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%... -
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uvmgen
Uvmgen is to generate the uvm frame codes for simulator
Uvmgen is to facilitate developing of uvm-based testbench. It provides the basic codes when you give the component info into uvmgen. I also provide the customized codes when you donate to the project. -
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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Jesta I.S. | Enterprise Software For Retail and Supply ChainUnify your people and operations across all departments and channels. Discover end-to-end retail, wholesale, and supply chain management software suites designed to scale.
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Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )
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xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
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ANVIL - (A)(N)other (V)erilog (I)nteraction (L)evel. C++ and VPI/C code to easily instrument RTL/Verilog (dut) and C++ testbench (tb) for more powerful and efficient verification (i.e., C++/tb drives simulator).
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This is the Ars TestBench 2.0 designed for evaluating various apsect of system performance created by members of ArsTechinca Open Forum.
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Pancham is an IP core that implements the MD5 message digest algorithm. It is written in Verilog and comes with a testbench. It will be portable across multiple simulators and will be synthesizable.
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Generic Safety CPU test framework
Generic CPU test programs and a testbench
...Additional to the test programs, the project includes a test framework consisting of a program calling the sub-test-programs and a TCL script which injects faults to verify the test programs. To run the TCL script, a user has to set up a testbench with Modelsim to simulate the HDL code of a CPU. The CPU runs the test programs and the TCL script injects faults into the CPU. -
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UVE
Unified Verification Environment
...This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. Files can be accessed easily by double clicking on the graphical view. Simulation can be launched directly from the tool.
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