Search Results for "sourceforge.net/projects/winpython/files/winpython_3.8/3.8.10.0/winpython64-3.8.10.0.7z" - Page 2
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Showing 86 open source projects for "sourceforge.net/projects/winpython/files/winpython_3.8/3.8.10.0/winpython64-3.8.10.0.7z"
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Powerful Website Security | Continuous Web Threat PlatformReflectiz is a comprehensive web exposure management platform that helps organizations proactively identify, monitor, and mitigate security, privacy, and compliance risks across their online environments. Designed to address the growing complexity of modern websites, Reflectiz provides full visibility and control over first, third, and even fourth-party components, such as scripts, trackers, and open-source libraries that often evade traditional security tools.
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The most trusted software in constructionHCSS provides easy-to-use software built for construction companies that want to win more work, work smarter, and boost profits. For nearly 40 years, we've helped heavy civil contractors, infrastructure builders, and utility companies improve operations, from estimating and project management to field tracking, equipment maintenance, and safety. Tools like HeavyBid, HeavyJob, and HCSS Safety are built for the field and designed to work together, giving your team real-time visibility, tighter cost control, and better job outcomes. With 45+ accounting integrations and customizable APIs, HCSS fits seamlessly into your tech stack. We regularly update our software based on feedback from real crews, ensuring it fits the way your team works. Backed by award-winning 24/7/365 support and a proven implementation process, HCSS helps reduce risk, cut inefficiencies, and deliver fast ROI. If you're ready to grow your business and gain a competitive edge, HCSS is the partner that gets you there.
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Timing-gen is a Linux tool to generate high quality Postscript timing diagrams from text input files.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
...However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags and rounded pads). -
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openCarac
openCarac : Automatize your Spice simulator runnings
openCarac aims to automatize the characterization of electronic circuits using your favourite Spice simulator and provide output files in HTML, LaTeX (c) and GNU Octave (c) scripts. openCarac is natively compatible with various simulators including: - Ngspice (c), http://ngspice.sourceforge.net - Gnucap (c), http://gnucap.org/dokuwiki/doku.php?id=gnucap:start - Xyce (c), http://xyce.sandia.gov It comes with an API which permits to add other features and extend openCarac compatibility; openCarac is also TCL package and comes with functions that can be called in any TCL script. ... -
Enterprise-Class Managed File Transfer.Diplomat MFT by Coviant Software is a secure, reliable managed file transfer solution designed to simplify and automate SFTP, FTPS, and HTTPS file transfers. Built for seamless integration, Diplomat MFT works across major cloud storage platforms, including AWS S3, Azure Blob, Google Cloud, Oracle Cloud, SharePoint, Dropbox, Box, and more.
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Cadence 614 Installer
Cadence 614 installing scripts with source files
this code include automation for installing Cadence614 with Calibre2011 all you need to do is to install Centos 6.5 32bit on your machine http://archive.kernel.org/centos-vault/6.5/isos/i386/CentOS-6.5-i386-LiveCD.iso and the scripts will do the rest -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. ... -
Parasoft: Automated Testing to Deliver Superior Quality SoftwareParasoft helps organizations continuously deliver high-quality software with its AI-powered software testing platform and automated test solutions. Supporting the embedded, enterprise, and IoT markets, Parasoft’s proven technologies reduce the time, effort, and cost of delivering secure, reliable, and compliant software by integrating everything from deep code analysis and unit testing to web UI and API testing, plus service virtualization and complete code coverage, into the delivery pipeline. Bringing all this together, Parasoft’s award-winning reporting and analytics dashboard provides a centralized view of quality, enabling organizations to deliver with confidence and succeed in today’s most strategic ecosystems and development initiatives—security, safety-critical, Agile, DevOps, and continuous testing.
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PerfDesign
Application for designing electronic based projects on perfboard.
PerfDesign is a small application for quickly designing or sketching your own projects on PERFBOARDs and STRIPBOARDs. -
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qtwavetool
Open Teradyne wave files (.wav)
Tool to open Teradyne ATE .wav files and view content in tabular form or plot and view graphically. -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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"ncdr2cnc" - N/C Drill to CNC code (G-Code) is the simple utility, which converts N/C drill files to G-Code files (adopted to Turbo CNC).
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Gerber Viewer(ipc2581viewer)
Gerber Drill IPC2581
View Gerber Files and Drill Files. View IPC-2581. -
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PCBColorizer
Automatic coloring PCB - make a color circuit board for installation.
The program is designed for automatic coloring schemes of printed circuit boards for ease of installation. For its work requires some files with information on the printed circuit board, package generated by P-CAD. The basic principle: each type of component (identical components) are marked with a unique symbol that has its own color and style. This simplifies the visual search component on the board. The program also generates a text list of components, where the marks, what type of components is associated with which character on the circuit board. -
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Spider PCB
Hierarchical Schematic and PCB
This project is in a pre-alpha stage and is intended to give a rough idea about the final program. It does not do much more than draw pretty pictures. Hierarchical circuit layout is commonplace amongst IC designers, but Spider PCB brings hierarchical layout to the PCB industry. Not only is the schematic hierarchical, but also the layout. Ever wanted to lay out a 16-band equaliser, with 5 sound channels? Lots of copying and pasting on the PCB-side. Just imagine if you could lay out one... -
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A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
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The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.
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CAPLET
GDS visualization and parallelized capacitance extraction
Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material. -
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FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
...Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit testing and physical test harness creation, radically changing the workflow. FPGAsm offers you an opportunity to REALLY understand Xilinx FPGAs, create circuits DIRECTLY on the FPGA using an opensource tool, and share your knowlege and projects with the community. Supported architectures: Xilinx (via xdl) -
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OpenETran
Electric power system transient simulator
...Since about 2002, this program has not been available. EPRI decided to release the simulation kernel of LPDW under an open-source license (GPL v3), so it may be incorporated into IEEE Flash and other projects. OpenETran can presently simulate multi-conductor power lines, insulators, surge arresters, non-linear grounds, and lightning strokes. It efficiently calculates energy and charge duty on surge arresters, and iterates to find the critical lightning current causing flashover on one or more phases. It is also suitable for use in substation insulation coordination. ... -
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...Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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A Step Closer to a Fully Gui ATLAS .log Converter A Gui .in Editor to be Used by ATLAS .log awk converter
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vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
