Search Results for "clock"
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Showing 2 open source projects for "clock"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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TotesNotes
Simple Popup Notes
...There are even a few tabs if you want to seperate them a little bit. * Requires .NET 4.5 Note : If you dont see the icon in your tray, just drag it next to your clock. It should stay there for future use. Feel free to add ideas and suggestions to the discussion group.
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