qucs-bugs Mailing List for Quite Universal Circuit Simulator

Hi，
<qucs-0.0.19 >
I'm trying to use "frequency" which system defined variable in equation like this: Yc=j*2*pi*frequency*1e-12 (means: j*omega*C, the "omega" is unvalid ), then use component "Equation Defined RF Device" choose Y-type and 2-port: p11=p22=Yc,p12=p21=-Yc, next add AC power source to do SP simulation: simulator crash, and errors & warnings is: checker error: no appropriate function for ' ((((0+j1)*2)*pi)*frequency)' found. evaluated error: no such generated variable 'frequency'. Can you help to fix it or how should I solve such problem in my Equation, thank.

I'm new to working with a group on Development and don't have a 
programming background, but have done a fair bit of debugging type 
programming (mostly in C, but also a lot in Python and some in golang 
and julia and a lot in Matlab), and am willing to learn. Below is an 
example of how I might post a bug report; could someone please tell me 
how I should properly format/fix it.

I have successfully compiled ngspice as long as I don't include adms; 
I'm not even close if I include adms. ngspice might be fine for my main 
objective (teaching), but Xyce looks to be a more "Real" simulator and 
one of my long term (can't be too long term or I might not be around) 
goals is to get to were I can generate from schematics netlists of 
verilog and verilogAMS. Also, it looks like Xyce is being well supported 
by Sandia Labs. Wouldn't it be nice if we could get verilog and 
verilogAMS into Xyce via hooking up to Verilator (well for verilog - any 
suggestions for getting verilogAMS going would be appreciated)

Platform: Ubuntu 20.04

Working On: Xyce 7.4

Directory: .../Xyce/Trilinos/MY_BUILD

This directory is on my work computer: I can't remember how I installed 
(it's not a github directory), my best guess is it came from a (*.gz 
file I downloaded - I will normalize to git hub and retry but it 
certainly came from somewhere real that is recent)

Maybe: I should report to Xyce but I am working on getting Xyce into 
Qucs-S and it's hard to have enough bandwidth to interact with two 
groups; for now I've chosen (as recommended by Felix Salfelder - 
https://github.com/felix-salfelder) to focus on Qucs-S.

Command: many commands and installs and then >make (this worked) and 
then >sudo make install

Output:

...

many many lines

...

[ 80%] Building CXX object 
packages/stk/stk_io/stk_io/CMakeFiles/stk_io.dir/WriteMesh.cpp.o
[ 80%] Linking CXX static library libstk_io.a
[ 80%] Built target stk_io
Scanning dependencies of target stk_io_util
[ 80%] Building CXX object 
packages/stk/stk_io/stk_io/util/CMakeFiles/stk_io_util.dir/Gmesh_STKmesh_Fixture.cpp.o
[ 80%] Linking CXX static library libstk_io_util.a
[ 80%] Built target stk_io_util
Scanning dependencies of target stk_unit_main
[ 80%] Building CXX object 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_main.dir/unit_main_lib/UnitTestMain.cpp.o
[ 80%] Linking CXX static library libstk_unit_main.a
[ 80%] Built target stk_unit_main
Scanning dependencies of target stk_unit_test_utils
[ 80%] Building CXX object 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/BulkDataTester.cpp.o
[ 80%] Building CXX object 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/FaceTestingUtils.cpp.o
[ 80%] Building CXX object 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/GeneratedMeshToFile.cpp.o
[ 80%] Building CXX object 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/ParallelGtestOutput.cpp.o
/media/martin/ssd1/Downloads/Xyce/Trilinos/packages/stk/stk_unit_test_utils/ParallelGtestOutput.cpp:6:10: 
fatal error: gtest/gtest-test-part.h: No such file or directory
     6 | #include "gtest/gtest-test-part.h"      // for TestPartResult
       |          ^~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** 
[packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/build.make:122: 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/ParallelGtestOutput.cpp.o] 
Error 1
make[1]: *** [CMakeFiles/Makefile2:14030: 
packages/stk/stk_unit_test_utils/CMakeFiles/stk_unit_test_utils.dir/all] 
Error 2
make: *** [Makefile:183: all] Error 2

Comment: I found gtest-test-part.h at 
https://github.com/trilinos/Trilinos/blob/master/commonTools/gtest/gtest/gtest.h

and will normalize to this repo and re-do but

Question: 1) Is this a real bug or just something stupid I'm doing.

2) Should this be something I report to this mailing list and if so, how 
should I change the report from above? or

3) Any suggestions? Again, this is my first report, so as much as 
anything else: How should I make reasonable bug reports?

Thanks helping me get started?

-Ken

-- 

www.granitesemi.com
Mobile: +1 (416) 897-1840

I'm hoping to be able to help out when I get up and running. I'm 
especially interested a) the schematic capture, b) the GUI, c) the 
netlister, and d) verilog-AMS. I have lots of circuit design experience 
but no programming experience at the level of putting an autogen package 
distribution together and I find the process of debugging configure and 
make errors daunting. I have Qucs-s running but can not get Xyce or 
ngspice going.

I'm on Ubuntu 20.04 and believe I have installed the prerequisites (this 
was not easy for me - if I ever get up and running I might also try to 
clean it up for Ubuntu). Anyways, here is my current problem I am 
stumped on and if anyone has suggestions, I appreciate them. I do plan 
to continue and put time in but right now I am stuck. Also, again, my 
programming experience is limited, so unfortunately I need a bit more 
explanation on how to do things than more experienced programmers. 
Thanks in advance.

 > admsXml admsva/bsimbulk.va -Iadmsva -e ../admst/ngspiceMakefile.am.xml
[info...] admsXml-2.3.0 (unknown) Jan 28 2022 09:27:37
[info...] [admsva/bsimbulk.va:190]: macro `STROBE2 has too many (3) 
arguments
[info...] [admsva/bsimbulk.va:190]: macro `STROBE2 has too many (3) 
arguments
[info...] [admsva/bsimbulk.va:242]: macro `STROBE2 has too many (3) 
arguments
[fatal..] [admsva/bsimbulk.va:242]:syntax error: (unknown)

I checked bsimbulk.va:242 (and will post the lines if it will help) but 
I can't see the syntax error. Has anyone recently been able include adms 
into either ngspice or Xyce for Qucs-s?

Simulation lancée le dim. 21. mars 2021 à 18:54:14:030

création du fichier topologique… done.
Starting /usr/bin/qucsator

project location:
modules to load: 0
factorycreate.size() is 0
factorycreate has registered:
parsing netlist...
checking netlist...
subcircuit root
   DC:DC1 Temp="26.85" reltol="0.001" abstol="1e-12A" vntol="1e-06V" 
saveOPs="no" MaxIter="150" saveAll="no" convHelper="none" Solver="CroutLU"
   TR:TR1 Type="lin" Start="0" Stop="0.01s" Points="500" 
IntegrationMethod="Trapezoidal" Order="2" InitialStep="1e-09s" 
MinStep="1e-16" MaxIter="150" reltol="0.001" abstol="1e-12A" 
vntol="1e-06V" Temp="26.85" LTEreltol="0.001" LTEabstol="1e-06" 
LTEfactor="1" Solver="CroutLU" relaxTSR="no" initialDC="yes" MaxStep="0"
   Vrect:V1 V1 gnd U="3.3V" TH="0.003s" TL="0.001s" Tr="1e-09s" 
Tf="1e-09s" Td="0.002
s"
   MOSFET:T_BSS123_1 V1 _net0 gnd gnd Type="nfet" Vt0="1" Kp="0.00637" 
Gamma="1.24" Phi="0.75" Lambda="0.000625" Rd="0.14" Rs="0.14" Rg="0" 
Is="8.5e-14" N="1" W="0.0001" L="0.0001" Ld="0" Tox="1e-07" 
Cgso="3.6e-08" Cgdo="3e-08" Cgbo="1.24e-07" Cbd="1.98e-11" 
Cbs="2.37e-11" Pb="0.8" Mj="0.46" Fc="0.5" Cjsw="0" Mjsw="0.33" Tt="0" 
Nsub="0" Nss="0" Tpg="1" Uo="600" Rsh="0" Nrd="1" Nrs="1" Cj="0" Js="0" 
Ad="0" As="0" Pd="0" Ps="0" Kf="0" Af="1" Ffe="1" Temp="26.85" Tnom="26.85"
   IProbe:I1 _net1 _net0
   R:R2 gnd V1 R="1e+06Ohm" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
   Vdc:V2 _net2 gnd U="12V"
   R:R1 _net1 _net2 R="1000Ohm" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
   VProbe:Pr1 _net1 _net2
netlist content
       1 MOSFET instances
       1 IProbe instances
       1 DC instances
       1 VProbe instances
       2 R instances
       1 Vrect instances
       1 Vdc instances
       1 TR instances
creating netlist...

Des erreurs ont été détectées pendant la simulation le dim. 21. mars 
2021 à 18:54:14:653
Abandon.

    Hello,

  A rather simple bug, just annoying: when placing a marquer on a Smith chart diagram to see the associated impedance (real/imaginary), Z0 is used for denormalisation. By default it is 50Ω and if modifying this value works, it is reset to 50Ω each time the file is re-open.

    Best Regards,

      Erwan Le Roux

Hi all,

I found out that this happens only with version 0.0.19 and higher. With the
version 0.0.18 it works well. I can run the rlc_series that you provided to
me. It doens't work on 0.0.19 and 0.020rc1. The simulator always crash with
the same message. It is likely because i am using Ubuntu.
Do you know if a new stable version is plan  for Ubuntu ?
Thanks.

Le jeu. 23 mai 2019 à 08:59, Alexandre Pottrain <apo...@gm...> a
écrit :

> Hi all,
>
> Thank you for your help. Indeed you are right for the V() <- statement in
> this RLC.va. So it could not work anyway. But actually it is not the issue
> here. The reason i tried this one is because the model of the MOSFET i had
> (which has no statement like this) had the same issue, so i tried this
> rlc.va whithout really look at it, sorry for this.
>
> So what i did now is to try  the RLC serie that you provided (enclosed
> here) but i have still exactly the same issue. The .va seems correct now
> and compatible with what is required by ADMS.
>
> line 4: checker error, invalid definition type `Vdc'
>
> line 5: checker error, invalid definition type `IProbe'
>
> line 6: checker error, invalid definition type `DC'
>
> double free or corruption (out)
>
>
> ERROR: Simulator crashed!
>
>
> By the way i tried the model of my MOSFET and this one that you provided
> on QUCSSTUDIO (on windows) and both worked like a charm. I know they are
> different but they used both ADMS for the model generation so why should it
> be different ? I also do not understand why i still have this issue with
> the RLC serie model that you provided ? I prefer to use Ubuntu, this is why
> i really want it to work on QUCS also.
>
>
> Thank you.
>
>
>
>
>
> Le mer. 22 mai 2019 à 21:47, Claudio Girardi <cla...@vi...>
> a écrit :
>
>> Hello,
>> unfortunately the list removed the attachment; please try copying into
>> into the email body or use pastebin or similar,
>>
>> regards,
>>   Claudio
>>
>> > Il 22 maggio 2019 alle 12.16 Alexandre Pottrain <apo...@gm...>
>> ha scritto:
>> >
>> >
>> > Hello,
>> >
>> > I am having fun using QUCS but i have an issue i am not able to solve.
>> I am
>> > trying to simulate a very simple verilog A module (rlc.va coming from
>> Xyce)
>> > (see attached). I compile it running ADMSxml in QUCS (i use qucs
>> > 0.0.20-rc1) and try to simulate it. However the DC simulation crash (it
>> was
>> > exactly the same with an other more complicated model) with this
>> message :
>> >
>> > line 4: checker error, invalid definition type `Vdc'
>> >
>> > line 6: checker error, invalid definition type `DC'
>> >
>> > double free or corruption (out)
>> >
>> >
>> > ERROR: Simulator crashed!
>> >
>> > Please report this error to quc...@li...
>> >
>> >
>> > I do not know what to do to solve this. Thank you for your help.
>> >
>> >
>> > Best Regards,
>> >
>> >
>> > Alex.
>> >
>> > _______________________________________________
>> > Qucs-bugs mailing list
>> > Quc...@li...
>> > https://lists.sourceforge.net/lists/listinfo/qucs-bugs
>>
>

Hi all,

Thank you for your help. Indeed you are right for the V() <- statement in
this RLC.va. So it could not work anyway. But actually it is not the issue
here. The reason i tried this one is because the model of the MOSFET i had
(which has no statement like this) had the same issue, so i tried this
rlc.va whithout really look at it, sorry for this.

So what i did now is to try  the RLC serie that you provided (enclosed
here) but i have still exactly the same issue. The .va seems correct now
and compatible with what is required by ADMS.

line 4: checker error, invalid definition type `Vdc'

line 5: checker error, invalid definition type `IProbe'

line 6: checker error, invalid definition type `DC'

double free or corruption (out)


ERROR: Simulator crashed!


By the way i tried the model of my MOSFET and this one that you provided on
QUCSSTUDIO (on windows) and both worked like a charm. I know they are
different but they used both ADMS for the model generation so why should it
be different ? I also do not understand why i still have this issue with
the RLC serie model that you provided ? I prefer to use Ubuntu, this is why
i really want it to work on QUCS also.


Thank you.





Le mer. 22 mai 2019 à 21:47, Claudio Girardi <cla...@vi...>
a écrit :

> Hello,
> unfortunately the list removed the attachment; please try copying into
> into the email body or use pastebin or similar,
>
> regards,
>   Claudio
>
> > Il 22 maggio 2019 alle 12.16 Alexandre Pottrain <apo...@gm...>
> ha scritto:
> >
> >
> > Hello,
> >
> > I am having fun using QUCS but i have an issue i am not able to solve. I
> am
> > trying to simulate a very simple verilog A module (rlc.va coming from
> Xyce)
> > (see attached). I compile it running ADMSxml in QUCS (i use qucs
> > 0.0.20-rc1) and try to simulate it. However the DC simulation crash (it
> was
> > exactly the same with an other more complicated model) with this message
> :
> >
> > line 4: checker error, invalid definition type `Vdc'
> >
> > line 6: checker error, invalid definition type `DC'
> >
> > double free or corruption (out)
> >
> >
> > ERROR: Simulator crashed!
> >
> > Please report this error to quc...@li...
> >
> >
> > I do not know what to do to solve this. Thank you for your help.
> >
> >
> > Best Regards,
> >
> >
> > Alex.
> >
> > _______________________________________________
> > Qucs-bugs mailing list
> > Quc...@li...
> > https://lists.sourceforge.net/lists/listinfo/qucs-bugs
>

Hello,
unfortunately the list removed the attachment; please try copying into into the email body or use pastebin or similar,

regards,
  Claudio

> Il 22 maggio 2019 alle 12.16 Alexandre Pottrain <apo...@gm...> ha scritto:
> 
> 
> Hello,
> 
> I am having fun using QUCS but i have an issue i am not able to solve. I am
> trying to simulate a very simple verilog A module (rlc.va coming from Xyce)
> (see attached). I compile it running ADMSxml in QUCS (i use qucs
> 0.0.20-rc1) and try to simulate it. However the DC simulation crash (it was
> exactly the same with an other more complicated model) with this message :
> 
> line 4: checker error, invalid definition type `Vdc'
> 
> line 6: checker error, invalid definition type `DC'
> 
> double free or corruption (out)
> 
> 
> ERROR: Simulator crashed!
> 
> Please report this error to quc...@li...
> 
> 
> I do not know what to do to solve this. Thank you for your help.
> 
> 
> Best Regards,
> 
> 
> Alex.
> 
> _______________________________________________
> Qucs-bugs mailing list
> Quc...@li...
> https://lists.sourceforge.net/lists/listinfo/qucs-bugs

Hello,

The Verilog-A construct V() <+ ; is not implemented in the Qucs ADMS
interface. Note that only a subset of the language is supported.
In most cases you can work around it by rewriting the equations. This might
be very difficult for complicated models.
Browse thru the available models on the source for more working examples.
In [1] you can find a simple RLC series circuit on which the inductor is
represented with a gyrator. Credit to Mike Brinson.
I tried to attach the zip file, but sourceforge is rejecting it based on
the extension...

Regards,
Guilherme

[1] https://drive.google.com/open?id=1OxKVVJtm81kyN132pzAsibZlUOr-SE1T

On Wed, May 22, 2019 at 8:47 PM Alexandre Pottrain <apo...@gm...>
wrote:

> Hello,
>
> I am having fun using QUCS but i have an issue i am not able to solve. I am
> trying to simulate a very simple verilog A module (rlc.va coming from
> Xyce)
> (see attached). I compile it running ADMSxml in QUCS (i use qucs
> 0.0.20-rc1) and try to simulate it. However the DC simulation crash (it was
> exactly the same with an other more complicated model) with this message :
>
> line 4: checker error, invalid definition type `Vdc'
>
> line 6: checker error, invalid definition type `DC'
>
> double free or corruption (out)
>
>
> ERROR: Simulator crashed!
>
> Please report this error to quc...@li...
>
>
> I do not know what to do to solve this. Thank you for your help.
>
>
> Best Regards,
>
>
> Alex.
>
> _______________________________________________
> Qucs-bugs mailing list
> Quc...@li...
> https://lists.sourceforge.net/lists/listinfo/qucs-bugs
>

Hello,

I am having fun using QUCS but i have an issue i am not able to solve. I am
trying to simulate a very simple verilog A module (rlc.va coming from Xyce)
(see attached). I compile it running ADMSxml in QUCS (i use qucs
0.0.20-rc1) and try to simulate it. However the DC simulation crash (it was
exactly the same with an other more complicated model) with this message :

line 4: checker error, invalid definition type `Vdc'

line 6: checker error, invalid definition type `DC'

double free or corruption (out)


ERROR: Simulator crashed!

Please report this error to quc...@li...


I do not know what to do to solve this. Thank you for your help.


Best Regards,


Alex.

Hi,
You must add a block from  Components>Simulations>  to run the simulation
engine.
Yes, the error message is not helpful.
Regards,
Guilherme


On Sun, Jan 13, 2019 at 1:41 PM Jérémy Hervé <jer...@gm...> wrote:

> Hello,
>
>
> I just ./configure ; make ; make install'ed Qucs and tried to follow the
> "Getting Started with Analog Simulations" tutorial available in the Qucs
> help system.
>
>
> After clicking on "Simulation->Simulate" menu item, it blithely displays :
>
>
> ERROR: Simulator crashed!
>
> Please report this error to quc...@li...
>
>
> I attached the corresponding schematics.
>
>
> Best regards,
>
> Jérémy Hervé
>
> _______________________________________________
> Qucs-bugs mailing list
> Quc...@li...
> https://lists.sourceforge.net/lists/listinfo/qucs-bugs
>

Hello,


I just ./configure ; make ; make install'ed Qucs and tried to follow the
"Getting Started with Analog Simulations" tutorial available in the Qucs
help system.


After clicking on "Simulation->Simulate" menu item, it blithely displays :


ERROR: Simulator crashed!

Please report this error to quc...@li...


I attached the corresponding schematics.


Best regards,

Jérémy Hervé

Hello

I am a circuit designer using QUCS version 0.0.19 for the first time and my main interest is in using Harmonic Balance (HB) and an optimizer to design an active MOSFET gate driver circuit.  For starters I downloaded the file diode_hb.sch<http://qucs.sourceforge.net/examples/diode_hb.sch> and it ran both in QUCS HB and transient SPICE simulator.  Then I tried to replace the diode with a diode-connected 2N2222 transistor and it crashed.  I am attaching a copy of the modified file.  Is there another transistor model I should be using instead of the one from the system libraries supplied with the software?  Should I modify some of the parameters in the HB block (more harmonics, looser tolerances, adding conductances etc.) to generally help it converge?

.........................
Best regards,
Paul Gili
603-769-1905

The deactivate component does not seem to work correctly when used with a
2-port file.  When it shows a green x over the file component it is not
deactivating the component as a short.  This may be the case with the other
file component types but I have only been using the 2-port.

hi all,

I've tried to check simulation NL versus measurements, previously this 
file was working but now it crashes for some reason ... any ideas.

qucs.0.0.19   from last github extract 
(qucs-git-373d7373a6f79e6ff6bbf76a814fedbde684b518)

working on xubuntu ( ubuntu latest release 18.04.LTS )


seems realted to the DC or non linear solver ... linear solver is working


thierry Scordilis.

I changed the default simulator to Quacsator and the error disappeared.
Kind regards,Arham
   On Thursday, August 23, 2018, 7:29:52 AM GMT+4:30, Arham Amouie <erh...@ya...> wrote:  
 
 Hi. I recently installed Qucs-S version 0.0.20. When I click the Simulate icon for some schematic, I receive these lines:

Ngspice started...

Original line no.: 7, new internal line no.: 13:

Undefined number [IB]

Original line no.: 7, new internal line no.: 13:

Cannot compute substitute




ERROR: fatal error in ngspice, exit(1)




Circuit: * qucs 0.0.20 /home/arham/.qucs/testparametersweep_prj/testparametersweep.sch




 Copies=14 Evals=14 Placeholders=1 Symbols=1 Errors=2

Here is the schematic, which is very closely based on Figure 26 (page 25) of A Tutorial Getting Started with Qucs by S. Jahn and J.C. Borras:

<Qucs Schematic 0.0.20>
<Properties>
  <View=0,0,854,800,1,0,0>
  <Grid=10,10,1>
  <DataSet=TestParameterSweep.dat>
  <DataDisplay=TestParameterSweep.dpl>
  <OpenDisplay=1>
  <Script=TestParameterSweep.m>
  <RunScript=0>
  <showFrame=0>
  <FrameText0=Title>
  <FrameText1=Drawn By:>
  <FrameText2=Date:>
  <FrameText3=Revision:>
</Properties>
<Symbol>
</Symbol>
<Components>
  <.SW SW1 1 640 50 0 77 0 0 "DC1" 1 "log" 1 "Ib" 1 "10 n" 1 "10 m" 1 "101" 1 "false" 0>
  <_BJT Q2N4401_1 1 340 190 8 -26 0 0 "npn" 0 "9.09e-15" 0 "1" 0 "1" 0 "0.36" 0 "0.54" 0 "113" 0 "24" 0 "1.06e-11" 0 "2" 0 "0" 0 "2" 0 "300" 0 "4" 0 "0" 0 "0" 0 "0.127" 0 "0.319" 0 "1.27" 0 "2.34e-11" 0 "0.75" 0 "0.33" 0 "1.02e-11" 0 "0.75" 0 "0.33" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "5.12e-10" 0 "0" 0 "0" 0 "0" 0 "1.51e-07" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.5" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0>
  <.DC DC1 1 90 410 0 46 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
  <Vdc V1 1 490 240 18 -26 0 1 "10" 1>
  <GND * 1 340 330 0 0 0 0>
  <Eqn Eqn1 1 650 350 -31 19 0 0 "Ic=-V1.I" 1 "Beta=Ic/Ib" 1 "yes" 0>
  <Idc I1 1 210 190 -26 18 0 0 "Ib" 1>
</Components>
<Wires>
  <120 310 340 310 "" 0 0 0 "">
  <340 220 340 310 "" 0 0 0 "">
  <340 110 340 160 "" 0 0 0 "">
  <490 270 490 310 "" 0 0 0 "">
  <340 310 490 310 "" 0 0 0 "">
  <340 110 490 110 "" 0 0 0 "">
  <490 110 490 210 "" 0 0 0 "">
  <340 310 340 330 "" 0 0 0 "">
  <120 190 120 310 "" 0 0 0 "">
  <120 190 180 190 "" 0 0 0 "">
  <240 190 310 190 "" 0 0 0 "">
</Wires>
<Diagrams>
</Diagrams>
<Paintings>
</Paintings>

And this is the produced netlist:
* Qucs 0.0.20 /home/arham/.qucs/TestParameterSweep_prj/TestParameterSweep.sch
.INCLUDE "/usr/share/qucs-s/xspice_cmlib/include/ngspice_mathfunc.inc"
* Qucs 0.0.20  /home/arham/.qucs/TestParameterSweep_prj/TestParameterSweep.sch
Q2N4401_1 _net1 _net0 0 QMOD_Q2N4401_1 AREA=1 TEMP=26.85
.MODEL QMOD_Q2N4401_1 npn (Is=9.09e-15 Nf=1 Nr=1 Ikf=0.36 Ikr=0.54 Vaf=113 Var=24 Ise=1.06e-11 Ne=2 Isc=0 Nc=2 Bf=300 Br=4 Rbm=0 Irb=0 Rc=0.127 Re=0.319 Rb=1.27 Cje=2.34e-11 Vje=0.75 Mje=0.33 Cjc=1.02e-11 Vjc=0.75 Mjc=0.33 Xcjc=1 Cjs=0 Vjs=0.75 Mjs=0 Fc=0.5 Tf=5.12e-10 Xtf=0 Vtf=0 Itf=0 Tr=1.51e-07 Kf=0 Af=1 Ptf=0 Xtb=1.5 Xti=3 Eg=1.11 Tnom=26.85 )
V1 _net1 0 DC 10
I1 0 _net0 DC {IB}
.control
echo "" > spice4qucs.cir.noise
echo "" > spice4qucs.cir.pz
dc ib 1e-08 0.01 9.90098e-05
let Ic=-VV1#branch
let Beta=Ic/Ib
write TestParameterSweep_dc.txt  Ic Beta
destroy all
reset

exit
.endc
.END

Kind regards,Arham Amouei
  

Hi. I recently installed Qucs-S version 0.0.20. When I click the Simulate icon for some schematic, I receive these lines:

Ngspice started...

Original line no.: 7, new internal line no.: 13:

Undefined number [IB]

Original line no.: 7, new internal line no.: 13:

Cannot compute substitute




ERROR: fatal error in ngspice, exit(1)




Circuit: * qucs 0.0.20 /home/arham/.qucs/testparametersweep_prj/testparametersweep.sch




 Copies=14 Evals=14 Placeholders=1 Symbols=1 Errors=2

Here is the schematic, which is very closely based on Figure 26 (page 25) of A Tutorial Getting Started with Qucs by S. Jahn and J.C. Borras:

<Qucs Schematic 0.0.20>
<Properties>
  <View=0,0,854,800,1,0,0>
  <Grid=10,10,1>
  <DataSet=TestParameterSweep.dat>
  <DataDisplay=TestParameterSweep.dpl>
  <OpenDisplay=1>
  <Script=TestParameterSweep.m>
  <RunScript=0>
  <showFrame=0>
  <FrameText0=Title>
  <FrameText1=Drawn By:>
  <FrameText2=Date:>
  <FrameText3=Revision:>
</Properties>
<Symbol>
</Symbol>
<Components>
  <.SW SW1 1 640 50 0 77 0 0 "DC1" 1 "log" 1 "Ib" 1 "10 n" 1 "10 m" 1 "101" 1 "false" 0>
  <_BJT Q2N4401_1 1 340 190 8 -26 0 0 "npn" 0 "9.09e-15" 0 "1" 0 "1" 0 "0.36" 0 "0.54" 0 "113" 0 "24" 0 "1.06e-11" 0 "2" 0 "0" 0 "2" 0 "300" 0 "4" 0 "0" 0 "0" 0 "0.127" 0 "0.319" 0 "1.27" 0 "2.34e-11" 0 "0.75" 0 "0.33" 0 "1.02e-11" 0 "0.75" 0 "0.33" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "5.12e-10" 0 "0" 0 "0" 0 "0" 0 "1.51e-07" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.5" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0>
  <.DC DC1 1 90 410 0 46 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
  <Vdc V1 1 490 240 18 -26 0 1 "10" 1>
  <GND * 1 340 330 0 0 0 0>
  <Eqn Eqn1 1 650 350 -31 19 0 0 "Ic=-V1.I" 1 "Beta=Ic/Ib" 1 "yes" 0>
  <Idc I1 1 210 190 -26 18 0 0 "Ib" 1>
</Components>
<Wires>
  <120 310 340 310 "" 0 0 0 "">
  <340 220 340 310 "" 0 0 0 "">
  <340 110 340 160 "" 0 0 0 "">
  <490 270 490 310 "" 0 0 0 "">
  <340 310 490 310 "" 0 0 0 "">
  <340 110 490 110 "" 0 0 0 "">
  <490 110 490 210 "" 0 0 0 "">
  <340 310 340 330 "" 0 0 0 "">
  <120 190 120 310 "" 0 0 0 "">
  <120 190 180 190 "" 0 0 0 "">
  <240 190 310 190 "" 0 0 0 "">
</Wires>
<Diagrams>
</Diagrams>
<Paintings>
</Paintings>

And this is the produced netlist:
* Qucs 0.0.20 /home/arham/.qucs/TestParameterSweep_prj/TestParameterSweep.sch
.INCLUDE "/usr/share/qucs-s/xspice_cmlib/include/ngspice_mathfunc.inc"
* Qucs 0.0.20  /home/arham/.qucs/TestParameterSweep_prj/TestParameterSweep.sch
Q2N4401_1 _net1 _net0 0 QMOD_Q2N4401_1 AREA=1 TEMP=26.85
.MODEL QMOD_Q2N4401_1 npn (Is=9.09e-15 Nf=1 Nr=1 Ikf=0.36 Ikr=0.54 Vaf=113 Var=24 Ise=1.06e-11 Ne=2 Isc=0 Nc=2 Bf=300 Br=4 Rbm=0 Irb=0 Rc=0.127 Re=0.319 Rb=1.27 Cje=2.34e-11 Vje=0.75 Mje=0.33 Cjc=1.02e-11 Vjc=0.75 Mjc=0.33 Xcjc=1 Cjs=0 Vjs=0.75 Mjs=0 Fc=0.5 Tf=5.12e-10 Xtf=0 Vtf=0 Itf=0 Tr=1.51e-07 Kf=0 Af=1 Ptf=0 Xtb=1.5 Xti=3 Eg=1.11 Tnom=26.85 )
V1 _net1 0 DC 10
I1 0 _net0 DC {IB}
.control
echo "" > spice4qucs.cir.noise
echo "" > spice4qucs.cir.pz
dc ib 1e-08 0.01 9.90098e-05
let Ic=-VV1#branch
let Beta=Ic/Ib
write TestParameterSweep_dc.txt  Ic Beta
destroy all
reset

exit
.endc
.END

Kind regards,Arham Amouei

This circuit will trigger an infinite loop if you attempt a transient
simulation.

https://imgur.com/P2fqVE6

AC and DC simulations work OK.

Running on Manjaro


Starting new simulation on dom 18. feb 2018 at 16:54:22:341


creating netlist... done.

Starting /usr/bin/qucsator


project location:

modules to load: 0

factorycreate.size() is 0

factorycreate has registered:

parsing netlist...

checking netlist...

netlist content

2 IProbe instances

1 DC instances

2 R instances

1 Vdc instances

creating netlist...


Errors occurred during simulation on dom 18. feb 2018 at 16:54:22:530

Aborted.


-- 
Gracias.

I tried emulating a very crude "s" curve equation (x/sqrt(1+x^2)) in the equation block and the simulator cannot simulate it.

See example:
Netlist
# Qucs 0.0.19 X:/ --- confidential path --- /TestCubeRoot.sch


R:R1 S_curve gnd R="1" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
Vrect:V1 V_rect gnd U="1 V" TH="50m" TL="50m" Tr="20m" Tf="20m" Td="10m"

EDD:D1 gnd S_curve V_rect gnd I1="D1.I1" Q1="D1.Q1" I2="D1.I2" Q2="D1.Q2"

 Eqn:EqnD1I1 D1.I1="v2/sqrt(1+V2^2)" Export="no"

 Eqn:EqnD1Q1 D1.Q1="0" Export="no"

 Eqn:EqnD1I2 D1.I2="0" Export="no"

 Eqn:EqnD1Q2 D1.Q2="0" Export="no"

.TR:TR1 Type="lin" Start="0" Stop="1" Points="1001" IntegrationMethod="Trapezoidal" Order="2" InitialStep="1 ns" MinStep="1e-16" MaxIter="150" reltol="0.001" abstol="1 pA" vntol="1 uV" Temp="26.85" LTEreltol="1e-3" LTEabstol="1e-6" LTEfactor="1" Solver="CroutLU" relaxTSR="no" initialDC="yes" MaxStep="0"



Screenshot of schematic:

How do I simulate an "s" curve?

Hello,

I got a "Segmentation fault (core dumped)" error during simulation.

Linux 4.12.10-2-zen #1 ZEN SMP PREEMPT Tue Sep 5 20:35:00 UTC 2017 x86_64
GNU/Linux


*qucsator -i netlist.txt -c*
project location:
modules to load: 0
factorycreate.size() is 0
factorycreate has registered:
parsing netlist...
checking netlist...
checker notice, variable `Out1.v' in equation `Out1dB' not yet defined
checker notice, variable `Out4.Vt' in equation `fourier' not yet defined
checker notice, variable `Out2.v' in equation `Out2dB' not yet defined
checker notice, variable `Out3.v' in equation `Out3dB' not yet defined
checker notice, variable `Out4.v' in equation `Out4dB' not yet defined
checker notice, variable `Out4.v' in equation `Out4Ph' not yet defined
checker notice, variable `In.v' in equation `InPh' not yet defined
checker notice, variable `In.v' in equation `IndB' not yet defined
checker notice, variable `V3' in equation `D1.Q3' not yet defined
checker notice, variable `V2' in equation `D1.Q2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.Q1' not yet defined
checker notice, variable `V1' in equation `D1.I1' not yet defined
checker notice, variable `V1' in equation `D1.I1' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
netlist content
      1 potentiometer instances
      1 AC instances
     10 C instances
      1 RFEDD instances
      1 DC instances
      1 L instances
     18 R instances
      4 EDD instances
      1 Vdc instances
      1 Vac instances
      1 TR instances
creating netlist...
checker notice, netlist OK



*qucsator -i netlist.txt*
project location:
modules to load: 0
factorycreate.size() is 0
factorycreate has registered:
parsing netlist...
checking netlist...
checker notice, variable `Out1.v' in equation `Out1dB' not yet defined
checker notice, variable `Out4.Vt' in equation `fourier' not yet defined
checker notice, variable `Out2.v' in equation `Out2dB' not yet defined
checker notice, variable `Out3.v' in equation `Out3dB' not yet defined
checker notice, variable `Out4.v' in equation `Out4dB' not yet defined
checker notice, variable `Out4.v' in equation `Out4Ph' not yet defined
checker notice, variable `In.v' in equation `InPh' not yet defined
checker notice, variable `In.v' in equation `IndB' not yet defined
checker notice, variable `V3' in equation `D1.Q3' not yet defined
checker notice, variable `V2' in equation `D1.Q2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.I2' not yet defined
checker notice, variable `V2' in equation `D1.I2' not yet defined
checker notice, variable `V1' in equation `D1.Q1' not yet defined
checker notice, variable `V1' in equation `D1.I1' not yet defined
checker notice, variable `V1' in equation `D1.I1' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
checker notice, variable `S' in equation `RF1.S21' not yet defined
netlist content
      1 potentiometer instances
      1 AC instances
     10 C instances
      1 RFEDD instances
      1 DC instances
      1 L instances
     18 R instances
      4 EDD instances
      1 Vdc instances
      1 Vac instances
      1 TR instances
creating netlist...
Segmentation fault (core dumped)

Thanks!

Regards, Sebastian

the simulations work if i use only one sweep at the time i press F2...


Starting new simulation on Tue 25. Apr 2017 at 18:17:17:196 

creating
netlist... done. 

Starting qucsator 

project location: 

modules to load:
0 

factorycreate.size() is 0 

factorycreate has registered: 

parsing
netlist... 

checking netlist... 

netlist content 

1 Iac instances 

1 AC
instances 

2 C instances 

4 BJT instances 

1 DC instances 

9 R
instances 

2 SW instances 

2 Vdc instances 

creating netlist... 

Errors
occurred during simulation on Tue 25. Apr 2017 at 18:17:17:987 

Aborted.


I use version 0.0.19 (unknown) on linux mint 64 v17.3

Hi,

I have big trubble with qucs 0.0.19.

Problem 1:
qucs crashed, when initial state of a switch in "off".
It works when initial state is "on".
Crash report below.

Problem 2:
When initial state is "on" and there are more than one time stamps for 
state changes, only the first one will be interpreted.

best regards
Fabian Hoemcke



_Progress:_
Starting new simulation on Do. 09. Mär 2017 at 17:08:33:535

creating netlist... done.
Starting /usr/bin/qucsator

project location:
modules to load: 0
factorycreate.size() is 0
factorycreate has registered:
parsing netlist...
checking netlist...
subcircuit root
   Vdc:V1 _net0 gnd U="1V"
   R:R1 gnd Output R="50Ohm" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
   C:C1 gnd Output C="0.001F"
   TR:TR1 Type="lin" Start="0" Stop="1.1s" Points="11001" 
IntegrationMethod="Trapezoidal" Order="2" InitialStep="1e-09s" 
MinStep="1e-16" MaxIter="150" reltol="0.001" abstol="1e-12A" 
vntol="1e-06V" Temp="26.85" LTEreltol="0.001" LTEabstol="1e-06" 
LTEfactor="1" Solver="CroutLU" relaxTSR="no" initialDC="yes" MaxStep="0"
   Switch:S1 _net0 Output init="off" time="[0.005;1]" Ron="0" 
Roff="1e+12" Temp="26.85" MaxDuration="1e-06" Transition="spline"
netlist content
       1 Switch instances
       1 C instances
       1 R instances
       1 Vdc instances
       1 TR instances
creating netlist...
NOTIFY: TR1: creating node list for initial DC analysis
NOTIFY: TR1: solving initial DC netlist
NOTIFY: TR1: creating node list for transient analysis
NOTIFY: TR1: solving transient netlist

Errors occurred during simulation on Do. 09. Mär 2017 at 17:08:33:649
Aborted.

_Errors and Warnings:_

qucsator: 
/build/qucs-DrDFvN/qucs-0.0.19.qucs-rc1/qucs-core/src/components/tswitch.cpp:196: 
virtual void tswitch::calcTR(double): Assertion `r >= ron' failed.

ERROR: Simulator crashed!

Please report this error to quc...@li...




-- 
Fabian Hoemcke, B.Eng.
Student
*Technische Universität Berlin*
Fachgebiet Elektronik und medizinische Signalverarbeitung
Sekretariat EN3
Einsteinufer 17
D-10587 Berlin

*Sekretariat*
Raum: EN538
Sekretärin: Elisabeth Schwidtal
Öffnungszeiten:
Mo - Di 10:30 - 12:00 Uhr und 14:00 - 15:00 Uhr,
Do - Fr 10:30 - 12:00 Uhr
Tel: +49(0)30 314-21391
Fax: +49(0)30 314-22120

Hello,
I think that the problem comes mainly from the fact that the circuit 
on the left of the transmission line does not have an explicit path to 
ground. If you connect it to ground via a (high-value) resistor it 
works fine.
I guess you may be on a 32 b machine, as the results I see here with 
the original circuit are different, still some point wrong but not as 
bad as yours...
Still it will be good to check the source code, feel free to fill a 
bug ticket as a reminder...

Regards,
  Claudio


>----Messaggio originale----
>Da: "sou...@yv..." <sou...@yv...>
>Data: 25-ago-2016 7.59 PM
>A: <quc...@li...>
>Ogg: [Qucs-bugs] [SPAM] S21 parameter are wrong for simple 
tranmission	lines
>
>Dears,
>
>Thanks a lot for this very nice simulation package. I think I’ve 
found a bug
>with S-parameter simulation of transmission lines.
>
>Even a simple model of an ideal transmission line does not provide 
correct results.
>
>I’ve setup 2 ports with 50 ohm impedance, connected to an ideal 
transmission
>line of 50 ohm.
>
>I calculate the dB value of S21 with the following equation: S21dB=dB
(S[2,1])
>which normally works fine in other simulation I made.
>
>I would expect S21= 0 dB, ( or corresponding to the alpha attenuation 
times the
>length if one set alpha <>0). But I get a strange varying result, 
between 0 and
>-6.02 dB instead, with even some values above 0dB, which is not 
coherent for
>passive circuits.
>
>I have placed the schematic and result files for download here (don’t 
know how
>long the link will stay valid):
>
>https://temp-share.
com/f/ktjolxqwfk/7112bebdc37feaa31d77c6ca754a3f26b7e19fa1fcce908a84f963ef28d7badf
>
>or below this mail as netlist.
>
>To be noted, I’ve seen the same behavior in both QUCS versions 0.0.17 
and 0.0.19
>
>Can somebody have a look at this issue?
>
>Shall I post a bug ticket? (I didn’t wanted to do so without 
confirmation from
>somebody else)
>
>Best Regards
>
># Qucs 0.0.19 C:/zzz/QUCS_Transmmission_line_bug.sch
>
>Pac:P1 _net0 _net1 Num="1" Z="50 Ohm" P="0 dBm" f="1 GHz" Temp="
26.85"
>
>Pac:P2 _net2 gnd Num="2" Z="50 Ohm" P="0 dBm" f="1 GHz" Temp="26.85"
>
>.SP:SP1 Type="lin" Start="1MHz" Stop="1GHz" Points="201" Noise="no" 
NoiseIP="1"
>NoiseOP="2" saveCVs="no" saveAll="no"
>
>TLIN4P:Line1 _net0 _net2 gnd _net1 Z="50 Ohm" L="10" Alpha="0 dB" 
Temp="26.85"
>
>Eqn:Eqn1 S11dB="dB(S[1,1])" S21dB="dB(S[2,1])" Export="yes"
>
>

>------------------------------------------------------------------------------
>_______________________________________________
>Qucs-bugs mailing list
>Quc...@li...
>https://lists.sourceforge.net/lists/listinfo/qucs-bugs
>

Hi,

I'm trying to do a Harmonic Balance of an amplifier but the simulator
is crashing. I tried to change the transistor but it is happening with all
transistors. Do you have any idea what is happening?

Best regards,

Wellington Amaral