Free VHDL Parser with Java, Python and T

This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has been bundled as an executable JAR file along with an application which reads a RTL file(s), dumps the design units and the reverts those back. Please refer to the document for the details of the available APIs. You need Java JRE 1.6.x or above in order to use this utility. Feel free to contact the support team for any assistance.