VHDL Design Verification Tools download

This project contains a set of tools for formal verification and static analysis of VHDL design.

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License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Languages

English

Intended Audience

Education

User Interface

Command-line

Programming Language

Python

Related Categories

Python UML Tool, Python Software Testing Tool, Python Compilers

Registered

2009-02-22

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